The present invention relates to a configuration of an MIS (Metal Insulator Semiconductor) field effect transistor, and particularly to a high voltage MIS field effect transistor having a high withstanding voltage. More particularly, the present invention relates to a technique for integrating a high voltage MIS field effect transistor with a control circuit section to a high density.
Conventionally, a planar cell structure shown in FIG. 17 has been adopted to integrate a high voltage MIS field effect transistor. The high voltage MIS field effect transistor shown in FIG. 17 is an n-channel-type MOSFET, in which drain regions 702, which are output terminal regions, are juxtaposed in parallel on an n-type semiconductor layer. The drain regions 702 are surrounded by an input terminal region 701 constituted by a source layer, gate electrodes, and the like. A drain pad opening portion 703 is formed at each of both ends of the drain region 702, and a wire is conductively connected to the drain pad opening portion 703 to control the MOSFET. With the MOSFET of the above-described configuration, however, it is necessary to secure a distance between adjacent ones of the drain regions 702 by not less than the width of the drain pad opening portion 703, so that limits exist for attaining high integration and low on-resistance of the device. Therefore, to achieve a higher degree of integration and permit low on-resistance, the input terminal region 701 and the output terminal region (drain region) 702 are formed in an interdigitated shape, an example of which is shown in FIG. 18. In the high voltage MOSFET, three drain regions 702a to 702c extend so as to branch off from the drain region 702 where the drain pad opening portion 703 is formed, and input terminal regions 701a and 701b are respectively formed between adjacent ones of these drain regions 702a to 702c. With the high voltage MOSFET having the above-described configuration, it is unnecessary to form drain pads in the respective comb-teeth-shaped drain regions 702a to 702c, making it possible to form the drain regions 702a to 702c with a narrow pitch. Since the enlargement of the channel width can be attained, it is possible to attain the high integration with a large current capacity and low on-resistance of the device.
With respect to such a technique of integrating a high voltage device, a further description will be given by referring to FIGS. 19(a) and 19(b). FIG. 19(a) is a plan view of a highly integrated MOSFET in which the input terminal region and the output terminal region are formed in an interdigitated shape in the same way as the high voltage MOSFET shown in FIG. 18 and FIG. 19(b) is a cross-sectional view thereof. This highly integrated, high voltage MOSFET is a horizontal type MOSFET manufactured by using a double diffusion method, and is called a horizontal-type DMOS. Referring first to the cross-sectional view shown in FIG. 19(b), a description will be given of this horizontal-type DMOS. In an n-type well layer 902 diffusion-formed on the obverse surface side of a p-type semiconductor substrate 901, a MOS section 925 is formed at one end thereof, while a drain section 926 is formed on another end thereof. In the MOS section 925, p-type base layers 903 constituting channel-forming layers are formed at both ends of a gate electrode 909. An n.sup.+ -type source layer 906 and a p.sup.+ -type base contact layer 905 are respectively formed in each of these base layers 903. The gate electrode 909 is formed in such a manner as to extend between the pair of source layers 906 via a gate oxide film 907 and over the base layers 903 and the well layer 902. A source electrode 910 abuts the source layer 906 and the base contact layer 905. The source electrode 910 has a field plate portion 910a which extends over an insulating film 915 toward a drain layer 908 which will be described later. Thus, the MOS section 925 has a structure in which the source layer 906 and the base layer 903 are double-diffused. In addition, the field plate portion 910a alleviates the concentration of an electric field at an end of the source layer 906, and a high voltage withstanding structure is thereby formed.
In the drain section 926, which is formed on the other end side of the well layer 902, the n.sup.+ -type drain layer 908 is formed on the surface of the well layer 902, and a drain electrode 911 abuts this drain layer 908. On the MOS section 925 side, this drain electrode 911 has a field plate portion 911a which projects over the insulating film 915 in a manner similar to that of the source electrode 910. Accordingly, the concentration of the electric field at the source layer 906 side end of the drain layer 908 is alleviated, and a high voltage withstanding structure is thereby formed.
Furthermore, in the horizontal-type DMOS, a p-type offset layer 904 is formed on the surface of the well layer 902 in such a manner as to extend between the base layer 903 and the drain layer 908, and the thick insulating film 915 is formed on this offset layer 904.
In such a horizontal-type DMOS, if a positive potential is applied to the gate electrode 909, the surface of the base layer 903 immediately below the gate electrode 909 becomes an n-type inverted layer, so that electrons, which are carriers, begin to flow from the source layer 906 to the well layer 902 via that inverted layer. These electrons flow downwardly on the lower side of the gate electrode 909, then flow in the horizontal direction along the well layer 902, and reach the drain layer 908 so as to be absorbed.
As shown in FIG. 19(a), the planar structure of the horizontal-type DMOS having the above-described construction is arranged such that a MOSFET section (the region indicated by T in the drawing), which is comprised of the MOS section 925, the source layer 906, and the drain section 926, is juxtaposed in parallel in the region of the well layer 902 formed on the semiconductor substrate 901 in the shape of a comb tooth. By repeating this comb tooth portion, the on-resistance of the device can be reduced, and the MOSFET section having a targeted on-resistance can be integrated in the same chip. The structure adopted is such that the concentration of an electric field caused by the wiring of a high-voltage wire is alleviated by adopting aerial wiring by providing a pad on each drain pad opening portion 914 and performing wire bonding with respect to the same.
In recent years, active development has been made of power integrated circuits (ICs) in which a power MOSFET capable of withstanding several hundred voltages or more and having a high-current output of several amperes and a control circuit section operating at a low voltage of about 5 V are incorporated in a single chip. As ICs for switching power sources, there are some which have already been realized. However, in order to realize such power ICs at low cost, a reduction in the chip size is essential. Accordingly, it is important to minimize the power MOSFET section which occupies a large area in the power IC.
Here, in the conventional horizontal-type DMOS described above with reference to FIGS. 19(a) and 19(b), in order to enhance the degree of integration of the device and reduce the on-resistance per unit area, it is necessary to reduce the width V of the drain layer 908 and the width U of the base layer 903 around the gate electrode 909. However, because of decreases in the radius of curvature due to reductions in the width V of the drain layer 908 and the width U of the base layer 903, the electric field is concentrated sharply in a drain corner portion 912 and in a base corner portion 913. The drain corner portion has a protruding shape in a plan view and located at a tip (terminating end) of the drain layer 908 extending toward the region of the MOS section 925. The base corner portion 913 has a protruding shape in a plan view and located at a tip (terminating end) of the base layer 903 projecting in correspondence to a recessed region, in a plan view, of the drain section 926. Consequently, there are problems in that the withstand voltage drops and the withstand voltage characteristic of the device deteriorates. Regarding the drop in withstand voltage, it has been confirmed by tests that in a case where the radius of curvature of the drain corner portion 912 and the base corner portion 913 is sufficiently large, a withstand voltage of 600 to 800 V is obtained, whereas if the radius of curvature is reduced to 5 to 30 .mu.m, the withstand voltage drops substantially to 100 to 300 V. In addition, in the high voltage MOSFET shown in FIG. 18, the concentration of the electric field also occurs at ends (protruding drain corner portions in a plan view) 812 of the input terminal regions 701a and 701b and at ends (protruding drain corner portions in a plan view) 809 of the output terminal regions 702a to 702c. Furthermore, it is necessary to take into account the concentration of the electric field at outer peripheral ends 814 of the drain pad 703, to which a strong electric field is applied. Also, there has been a possibility that the withstand voltage is rate-determined by these portions.